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V436416S04V(C)TG-75 3.3 VOLT 16M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SDRAM MODULE PRELIMINARY CILETIV LESOM Features tCK tAC Description The V436416S04V(C)TG-75 memory module is organized 16,777,216 x 64 bits in a 168 pin dual in line memory module (DIMM). The 16M x 64 memory module uses 16 Mosel-Vitelic 8M x 8 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. s 168 Pin Unbuffered 16,777,216 x 64 bit Oganization SDRAM DIMMs s Utilizes High Performance 8M x 8 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Specification s Single +3.3V ( 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 4096 Refresh Cycles every 64 ms s Serial Present Detect (SPD) s SDRAM Performance Component Used Clock Frequency (max.) Clock Access Time CAS Latency = 3 -7 143 5.4 Units MHz ns s Supported Latencies at 133 MHz Operation CL 3 tRCD 3 tRP 3 tRC 8 CLK V436416S04V(C)TG-75-01 V436416S04V(C)TG-75 Rev. 1.7 September 2001 1 V436416S04V(C)TG-75 CILETIV LESOM Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Pin Configurations (Front Side/Back Side) Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC Notes: * These pins are not used in this module. Pin Names A0-A11 I/O1-I/O64 RAS CAS WE BA0, BA1 CKE0, CKE1 CS0-CS3 CLK0-CLK3 DQM0-DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect SDA SA0-A2 CB0-CB1 NC DU Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don't Use V436416S04V(C)TG-75 Rev. 1.7 September 2001 2 V436416S04V(C)TG-75 CILETIV LESOM V MOSEL-VITELIC MANUFACTURED SDRAM Part Number Information 4 3 64 16 S 0 4 V C T G 75 133 MHz (PC133 3-3-3) GOLD TSOP 3.3V WIDTH DEPTH 168 PIN UNBUFFERED DIMM X 8 COMPONENT LVTTL 4 BANKS REFRESH RATE 4K V436416S04V(C)TG-75-02 Component Rev: Blank--B Rev C--C Rev Block Diagram CS1 CS0 DQM0 I/O1-I/O8 10 DQM1 I/O9-I/O16 10 CS3 CS2 DQM2 I/O17-I/O24 10 DQM3 I/O25-I/O32 10 E2PROM SPD (256 WORD X 8 BIT) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA VDD WP 47K DQM CS I/O1-I/O8 D0 DQM CS I/O1-I/O8 D1 DQM CS I/O1-I/O8 D8 DQM CS I/O1-I/O8 D9 DQM4 I/O33-I/O40 10 DQM5 I/O41-I/O48 10 DQM CS I/O1-I/O8 D4 DQM CS I/O1-I/O8 D5 DQM CS I/O1-I/O8 D12 DQM CS I/O1-I/O8 D13 CS DQM I/O1-I/O8 D2 DQM I/O1-I/O8 CS D3 CS DQM I/O1-I/O8 D10 DQM I/O1-I/O8 D11 CS DQM6 I/O49-I/O56 10 DQM7 I/O57-I/O64 10 CS DQM I/O1-I/O8 D6 CS DQM I/O1-I/O8 D7 CS DQM I/O1-I/O8 D14 CS DQM I/O1-I/O8 D15 A11-A0, BA0, BA1 C0-C31 D0-D15 D0-D15 D0-D7 D0-D15 VCC 10K D0-D7 VSS RAS, CAS, WE CKE0 CLOCK WIRING 16M X 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF 4 SDRAM +3.3pF CKE1 D9-D15 V436416S04V(C)TG-75-03 V436416S04V(C)TG-75 Rev. 1.7 September 2001 3 V436416S04V(C)TG-75 written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) E2PROM CILETIV LESOM Byte Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Serial Presence Detect Information A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is SPD-Table for PC133 modules: Hex Value Function Described Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS SPD Entry Value 128 256 SDRAM 12 9 2 64 0 LVTTL 7.5 ns 5.4 ns none Self-Refresh, 15.6s x8 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full Page 4 CL = 2, 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol 10% 10.0 ns 6.0 ns Not Supported Not Supported 20 ns 15 ns 20 ns 45 ns 16Mx64 80 08 04 0C 09 02 40 00 01 75 54 00 80 08 00 01 8F 04 06 01 01 00 0E A0 60 00 00 14 0F 14 2D V436416S04V(C)TG-75 Rev. 1.7 September 2001 4 V436416S04V(C)TG-75 CILETIV LESOM Byte Number 31 32 33 34 35 62-61 62 63 64 65-71 72 73-90 91-92 93 94 95-98 99-125 126 127 128+ Reserved Reserved SPD-Table for PC133 modules: (Continued) Hex Value Function Described Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number 00 64 00 00 V436416S04V(C)TG-75 Mosel Vitelic Revision 2 SPD Entry Value 64 MByte 1.5 ns 0.8 ns 1.5 ns 0.8 ns 16Mx64 10 15 08 15 08 00 02 8F 40 00 Intel Specification for Frequency Unused Storage Location DC Characteristics TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V Limit Values Symbol VIH V IL V OH VOL II(L) IO(L) Parameter Input High Voltage Input Low Voltage Output High Voltage (IOUT = -2.0 mA) Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC) Min. 2.0 -0.5 2.4 -- -10 Max. VCC +0.3 0.8 -- 0.4 10 Unit V V V V A A -10 10 V436416S04V(C)TG-75 Rev. 1.7 September 2001 5 V436416S04V(C)TG-75 Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. CILETIV LESOM Capacitance TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz Symbol CI1 CI2 CICL CI3 CI4 CIO CSC CSD Limit Values Parameter Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0-CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance (SA0-SA2) Max. 16M x 64 60 30 22 50 15 15 8 10 Unit pF pF pF pF pF pF pF pF Operating Currents TA = 0C to 70C, VCC = 3.3V 0.3V (Recommended operating conditions otherwise noted) Max. Symbol ICC1 Parameter & Test Condition Operating Current tRC = tRCMIN., tRC = tCKMIN. Active-precharge command cycling, without Burst Operation Precharge Standby Current in Power Down Mode CS =VIH , CKE VIL(max) 1 bank operation -75 1040 Unit mA Note 7 ICC2P tCK = min. tCK = Infinity 32 mA 7 ICC2PS ICC2N Precharge Standby Current in Non-Power Down Mode CS =VIH , CKE VIL(max) 16 320 mA mA 7 tCK = min. tCK = Infinity ICC2NS ICC3 No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) 40 400 mA mA CKE VIH(MIN.) CKE VIL(MAX.) (Power down mode) ICC3P 64 mA ICC4 Burst Operating Current tCK = min Read/Write command cycling Auto Refresh Current tCK = min Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE=0.2V 640 mA 7,8 ICC5 1120 mA 7 ICC6 16 L-version 8 mA mA V436416S04V(C)TG-75 Rev. 1.7 September 2001 6 V436416S04V(C)TG-75 CILETIV LESOM AC Characteristics TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns -75 # Symbol Parameter Min. Clock and Clock Enable 1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition Tim 7.5 10 2 tCK - - 3 tAC - _ 2.5 2.5 0.3 4 5 6 tCH tCL tT Limit Values Max. Unit Note - - s ns ns 133 100 MHz MHz 2, 4 5.4 6 - - 1.2 ns ns ns ns ns Setup and Hold Times 7 8 9 10 11 12 tIS tIH tCKS tCKH tRSC tSB Input Setup Time Input Hold Time Input Setup Time CKE Hold Time Mode Register Set-up Time Power Down Mode Entry Time 1.5 0.8 1.5 0.8 15 0 - - - - - 7.5 ns ns ns ns ns ns 5 5 5 5 Common Parameters 13 14 15 16 17 18 tRCD tRP tRAS tRC tRRD tCCD Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period 20 20 45 60 15 1 - - 100K - - - ns ns ns ns ns CLK 6 6 6 6 6 Refresh Cycle 19 20 tREF tSREX Refresh Period (4096 cycles) Self Refresh Exit Time -- 64 ms ns 10 V436416S04V(C)TG-75 Rev. 1.7 September 2001 7 V436416S04V(C)TG-75 CILETIV LESOM AC Characteristics TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns (Continued) -75 # Symbol Parameter Min. Read Cycle 21 22 23 24 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 2.7 1 - - Limit Values Max. Unit Note - - 5.4 2 ns ns ns CLK 2 7 Write Cycle 25 26 tWR tDQW Write Recovery Time DQM Write Mask Latency 1 0 - - CLK CLK V436416S04V(C)TG-75 Rev. 1.7 September 2001 8 V436416S04V(C)TG-75 CILETIV LESOM Notes: tCH 2.4V CLOCK 0.4V 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF INPUT 1.4V tCL tSETUP tHOLD tT tAC tLZ tOH tAC I/O 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. V436416S04V(C)TG-75 Rev. 1.7 September 2001 9 V436416S04V(C)TG-75 1 3.0 10 11 40 41 84 42.18 66.68 A B C 19.82 29.30 4.0 0.100 3.125 3.125 2.4 min. CILETIV LESOM 11. tDAL is equivalent to tDPL + tRP. Package Diagram SDRAM DIMM Module Package All measurements in mm. 133.35 (4.0 max) 127.35 1.27 0.100 85 94 95 124 125 168 D 6.35 6.35 1.27 1.0 0.05 0.2 0.15 2.0 Detail A Detail B 2.0 Detail C Tolerances: (0.13) unless otherwise specified. V436416S04V(C)TG-75 Rev. 1.7 September 2001 10 V436416S04V(C)TG-75 CILETIV LESOM Label Information MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) V436416S04VCTG-75 PC133U-333-542-A Taiwan XXXX-XXXXXXX DIMM manufacture date code Trace Code PC133 U - 333 - 54 2 - A UNBUFFERED DIMM CL = 3 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) Gerber file Intel(R) PC100 x 8 Based JEDEC SPD Revision 2.0 tAC = 5.4 ns V436416S04V(C)TG-75-05 V436416S04V(C)TG-75 Rev. 1.7 September 2001 11 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 V436416S04V(C)TG-75 UK & IRELAND SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CILETIV LESOM SINGAPORE 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 JAPAN ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES SOUTHWESTERN 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-352-3775 FAX: 214-904-9029 (c) Copyright , MOSEL VITELIC Inc. Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 |
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